Yesterday Framework unveiled a small form factor desktop based on Halo Strix.
Halo strix seems to require memory with high bandwidth, specifically 256-bit LPDDR5x, according to the specs.
Allegedly, the company said they tried to find a solution to use modular memory (e.g. lpcamm) but it did not work out signal integrity wise (@36:10, from the unveiling video above and here.)
So I’m wondering exactly, why not?
It seems LPCAMM2, offers a 128-bits bus and can scale today up to 7500-8500 MT/s.
This would offer 7500 x 128 / 8 = 120GB/s. Would it not have been possible to simply place two LPCAMM2 modules, to cover the full extent of the 256-bit bus and reach the 256 GB/s, by using the 8000 MT/s configuration?
Did they reach integrity issues because they tried to reach the speeds using only one LPCAMM2 stick? That would indeed have been impossible. Maybe LPCAMM2 can not be combined (perhaps due to space as they are using the mini-ITX motherboard format)? Or am I missing something?
I was trying to reason from how GPUs occasionally use a so called clamshell design where, if I understand correctly, they split their bus to reach double the number of memory chips. The chips are paired and respond to the same addresses but then each provide part of the data which is then combined.
Your example for vehicles got me confused, because as you point out, if you double the number of lanes while keeping the speed the same, you do effectively double the number of vehicles passing per unit of time, which is the bandwidth we are trying to achieve.
I’m sorry if I’m missing some important details but I am still rather confused.
PS: as per the specific framework memory speed specs, the halo strix chip maxes out at 8000, so 8533 is not supported, as per the specs I linked in the the post.