The IR is designed to be easy to optimize, not easy for a real machine to execute. Among other things, it assumes it has access to an infinite number of registers so that it never needs to (and in fact is not allowed to) write a new value into a previously used register.
Thanks. It sounds like an interesting architecture to look into how the rest is abstracted within the CPU basics like ALU, timers, flags, and interrupts
It’s not really an architecture that is intended to map into anything in existing hardware, but having said that, Mill Computing is working on a new extremely unconventional architecture that is a lot closer to this; you can read more about it here, and specifically the design of the register file (which resembles a convener belt) is discussed here.
https://en.wikipedia.org/wiki/LLVM#Intermediate_representation
Probably a silly question, but why isn’t this intermediate representation of LLVM created in hardware, or is it?
The IR is designed to be easy to optimize, not easy for a real machine to execute. Among other things, it assumes it has access to an infinite number of registers so that it never needs to (and in fact is not allowed to) write a new value into a previously used register.
Thanks. It sounds like an interesting architecture to look into how the rest is abstracted within the CPU basics like ALU, timers, flags, and interrupts
It’s not really an architecture that is intended to map into anything in existing hardware, but having said that, Mill Computing is working on a new extremely unconventional architecture that is a lot closer to this; you can read more about it here, and specifically the design of the register file (which resembles a convener belt) is discussed here.
I don’t understand your question.